Datasheet

Byte Data Link Controller Module
Functional Description
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Figure 122 J1850 VPW BREAK Symbol
Valid BREAK
Symbol
If the next active to passive transition does not occur until after T
rv6(Min)
,
the current symbol will be considered a valid BREAK symbol. A BREAK
symbol should be followed by a SOF symbol beginning the next
message to be transmitted onto the J1850 bus. See Figure 122.
Message
Arbitration
Message arbitration on the J1850 bus is accomplished in a
non-destructive manner, allowing the message with the highest priority
to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wishes to transmit onto the J1850 bus, but detects that
another message is in progress, it automatically waits until the bus is
idle. However, if multiple nodes begin to transmit in the same
synchronization window, message arbitration will occur beginning with
the first bit after the SOF symbol and continue with each bit thereafter.
The VPW symbols and J1850 bus electrical characteristics are carefully
chosen so that a logic zero (active or passive type) will always dominate
over a logic one (active or passive type) simultaneously transmitted.
Hence logic zeroes are said to be ‘dominant’ and logic ones are said to
be ‘recessive’.
Whenever a node transmits a recessive bit and detects a dominant bit,
it loses arbitration, and immediately stops transmitting. This is known as
‘bitwise arbitration’.The loss of arbitration flag (in DLCBSVR) is set when
arbitration is lost. If the interrupt enable bit (IE in DLCBCR1) is set, an
interrupt request from the BDLC is generated. Reading the DLCBSVR
register will clear this flag.
(2) Valid BREAK Symbol
240µs
T
rv6(Min)
Active
Passive
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Freescale Semiconductor, Inc.
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