Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Figure 121 J1850 VPW Active Symbols
Invalid Active Bit If the active to passive transition beginning the next data bit or symbol
occurs between the passive to active transition beginning the current
data bit or symbol and T
rva2(Min)
, the current bit would be invalid. See
Figure 121(1).
Valid Active Logic
One
If the active to passive transition beginning the next data bit or symbol
occurs between T
rva2(Min)
and T
rva2(Max)
, the current bit would be
considered a logic one. See Figure 121(2).
Valid Active Logic
Zero
If the active to passive transition beginning the next data bit or symbol
occurs between T
rva1(Min)
and T
rva1(Max)
, the current bit would be
considered a logic zero.See Figure 121(3).
Valid SOF Symbol If the active to passive transition beginning the next data bit or symbol
occurs between T
rva3(Min)
and T
rva3(Max)
, the current symbol would be
considered a valid SOF symbol. See Figure 121(4).
T
rva2(Min)
T
rva1(Min)
T
rva1(Max)
T
rva2(Max)
T
rva2(Min)
(1) Invalid Active Bit
(2) Valid Active Logic One
(3) Valid Active Logic Zero
64µs
128µs
T
rva3(Min)
T
rva3(Max)
(4) Valid SOF Symbol
200µs
Active
Passive
Active
Passive
Active
Passive
Active
Passive
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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