Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Invalid Passive Bit If the passive to active transition beginning the next data bit or symbol
occurs between the active to passive transition beginning the current
data bit or symbol and T
rvp1(Min)
, the current bit would be invalid. See
Figure 119(1).
Figure 119 J1850 VPW Passive Symbols
Valid Passive Logic
Zero
If the passive to active transition beginning the next data bit or symbol
occurs between T
rvp1(Min)
and T
rvp1(Max)
, the current bit would be
considered a logic zero.See Figure 119(2).
Valid Passive Logic
One
If the passive to active transition beginning the next data bit or symbol
occurs between T
rvp2(Min)
and T
rvp2(Max)
, the current bit would be
considered a logic one. See Figure 119(3).
T
rvp1(Min)
T
rvp2(Min)
T
rvp2(Max)
T
rvp1(Max)
T
rvp1(Min)
(1) Invalid Passive Bit
(2) Valid Passive Logic Zero
(3) Valid Passive Logic One
64µs
128µs
T
rvp3(Min)
T
rvp3(Max)
(4) Valid EOD Symbol
200µs
Active
Passive
Active
Passive
Active
Passive
Active
Passive
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...