Datasheet

Byte Data Link Controller Module
Functional Description
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
The min and max symbol limits shown in the following sections (Invalid
Passive Bit to Valid BREAK Symbol) and figures (Figure 119 –
Figure 122) refer to the values listed in Tables 108 through 113.
7 End of Frame (EOF) T
rv4
60 70 74 t
bdlc
8 Inter-Frame Separator (IFS) T
rv5
75 --- --- t
bdlc
9 Break Signal (BREAK) T
rv6
60 --- --- t
bdlc
NOTE:
1. The receiver symbol timing boundaries are subject to an uncertainty of 1 t
bdlc
due to sampling considerations.
Table 113 BDLC Receiver VPW 4X Symbol Timing for Binary
Frequencies
Number Characteristic
Symbol
1
Min Typ Max Unit
1 Passive Logic 0 T
rvp1
91725t
bdlc
2 Passive Logic 1 T
rvp2
26 34 42 t
bdlc
3 Active Logic 0 T
rva1
26 34 42 t
bdlc
4 Active Logic 1 T
rva2
91725t
bdlc
5 Start of Frame (SOF) T
rva3
43 53 62 t
bdlc
6 End of Data (EOD) T
rvp3
43 53 62 t
bdlc
7 End of Frame (EOF) T
rv4
63 74 78 t
bdlc
8 Inter-Frame Separator (IFS) T
rv5
79 --- --- t
bdlc
9 Break Signal (BREAK) T
rv6
63 --- --- t
bdlc
NOTE:
1. The receiver symbol timing boundaries are subject to an uncertainty of 1 t
bdlc
due to sampling considerations.
Table 112 BDLC Receiver VPW 4X Symbol Timing for Integer
Frequencies
Number Characteristic
Symbol
1
Min Typ Max Unit
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