Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Table 111 BDLC Receiver VPW Symbol Timing for Binary
Frequencies
Number Characteristic
Symbol
1
Min Typ Max Unit
1 Passive Logic 0 T
rvp1
34 67 100 t
bdlc
2 Passive Logic 1 T
rvp2
101 134 171 t
bdlc
3 Active Logic 0 T
rva1
101 134 171 t
bdlc
4 Active Logic 1 T
rva2
34 67 100 t
bdlc
5 Start of Frame (SOF) T
rva3
172 210 251 t
bdlc
6 End of Data (EOD) T
rvp3
172 210 251 t
bdlc
7 End of Frame (EOF) T
rv4
252 293 314 t
bdlc
8 Inter-Frame Separator (IFS) T
rv5
315 --- --- t
bdlc
9 Break Signal (BREAK) T
rv6
252 --- --- t
bdlc
NOTE:
1. The receiver symbol timing boundaries are subject to an uncertainty of 1 t
bdlc
due to sampling considerations.
Table 112 BDLC Receiver VPW 4X Symbol Timing for Integer
Frequencies
Number Characteristic
Symbol
1
Min Typ Max Unit
1 Passive Logic 0 T
rvp1
81623t
bdlc
2 Passive Logic 1 T
rvp2
24 32 40 t
bdlc
3 Active Logic 0 T
rva1
24 32 40 t
bdlc
4 Active Logic 1 T
rva2
81623t
bdlc
5 Start of Frame (SOF) T
rva3
41 50 59 t
bdlc
6 End of Data (EOD) T
rvp3
41 50 59 t
bdlc
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