Datasheet

Byte Data Link Controller Module
Functional Description
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
.
Table 109 BDLC Transmitter VPW Symbol Timing for Binary
Frequencies
Number Characteristic Symbol Min Typ Max Unit
1 Passive Logic 0 T
tvp1
65 67 69 t
bdlc
2 Passive Logic 1 T
tvp2
132 134 136 t
bdlc
3 Active Logic 0 T
tva1
132 134 136 t
bdlc
4 Active Logic 1 T
tva2
65 67 69 t
bdlc
5 Start of Frame (SOF) T
tva3
208 210 212 t
bdlc
6 End of Data (EOD)
1
T
tvp3
170 172 174 t
bdlc
7 End of Frame (EOF)
1
T
tv4
250 252 254 t
bdlc
8 Inter-Frame Separator (IFS)
1
T
tv5
313 315 317 t
bdlc
NOTE:
1. The transmitter timing for this symbol depends upon the minimum detection
time of the symbol by the receiver.
Table 110 BDLC Receiver VPW Symbol Timing for Integer
Frequencies
Number Characteristic
Symbol
1
Min Typ Max Unit
1 Passive Logic 0 T
rvp1
32 64 95 t
bdlc
2 Passive Logic 1 T
rvp2
96 128 163 t
bdlc
3 Active Logic 0 T
rva1
96 128 163 t
bdlc
4 Active Logic 1 T
rva2
32 64 95 t
bdlc
5 Start of Frame (SOF) T
rva3
164 200 239 t
bdlc
6 End of Data (EOD) T
rvp3
164 200 239 t
bdlc
7 End of Frame (EOF) T
rv4
240 280 299 t
bdlc
8 Inter-Frame Separator (IFS) T
rv5
300 --- --- t
bdlc
9 Break Signal (BREAK) T
rv6
240 --- --- t
bdlc
NOTE:
The receiver symbol timing boundaries are subject to an uncertainty of 1 t
bdlc
due to sampling considerations.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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