Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
integer bus frequencies (CLKS = 0) and binary bus frequencies (CLKS
= 1), respectively.
The values specified in the tables are for the symbols appearing on the
SAE J1850 bus. These values assume the BDLC is communicating on
the SAE J1850 bus using an external analog transceiver, and that the
BDLC analog roundtrip delay value programed into the DLCBARD
register is the appropriate value for the transceiver being used. If these
conditions are not met, the symbol timings being measured on the SAE
J1850 bus will be significantly affected. For a detailed description of how
symbol timings are measured on the SAE J1850 bus, refer to the
appropriate SAE documents.
Table 108 BDLC Transmitter VPW Symbol Timing for Integer
Frequencies
Number Characteristic Symbol Min Typ Max Unit
1 Passive Logic 0 T
tvp1
62 64 66 t
bdlc
2 Passive Logic 1 T
tvp2
126 128 130 t
bdlc
3 Active Logic 0 T
tva1
126 128 130 t
bdlc
4 Active Logic 1 T
tva2
62 64 66 t
bdlc
5 Start of Frame (SOF) T
tva3
198 200 202 t
bdlc
6 End of Data (EOD)
1
T
tvp3
162 164 166 t
bdlc
7 End of Frame (EOF)
1
T
tv4
238 240 242 t
bdlc
8 Inter-Frame Separator (IFS)
1
T
tv5
298 300 302 t
bdlc
NOTE:
1. The transmitter timing for this symbol depends upon the minimum detection
time of the symbol by the receiver.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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