Datasheet

Byte Data Link Controller Module
Functional Description
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
(t
bdlc
) an apparent separation in these maximum time/minimum time
concurrences equal to one cycle of t
bdlc
occurs.
This one clock resolution allows the BDLC to properly differentiate
between the different bits and symbols, without reducing the valid
window for receiving bits and symbols from transmitters onto the J1850
bus having varying oscillator frequencies.
In VPW bit encoding, the tolerances for the both passive and active data
bits and symbols are defined with no gaps between definitions. For
example, the maximum length of a passive logic zero is equal to the
minimum length of a passive logic one, and the maximum length of an
active logic zero is equal to the minimum length of a valid SOF symbol.
Transmit and
Receive Symbol
Timing
Specifications
Tables 108 through 113 contain the SAE J1850 transmit and receive
symbol timing specifications for the BDLC. The units used in these
tables are mux interface clock periods (t
bdlc
). The mux interface clock is
a divided down version of the IP bus clock input to the module (see
BDLC Rate Select Register (DLCBRSR)). The mux interface clock
drives the transmit and receive counters which control symbol
generation and identification. The symbol timing in effect during J1850
operations is dependent the state of two control bits: the CLKS bit
DLCBCR1, which indicates whether the IP bus clock is an integer
frequency or a binary frequency; the RX4XE bit in DLCBCR2, which is
used to select 4X receiver operation.
Tables 108 and 110 indicate the transmit and receive timing for integer
IP bus frequencies (CLKS = 0) and 4X receive operation disabled
(RX4XE = 0). It is assumed that for integer bus frequencies the divided
down mux interface clock frequency will be 1MHz (t
bdlc
= 1 µs).
Tables 109 and 111 indicated the transmit and receive timing for binary
IP bus frequencies (CLKS = 1) and 4X receive operation disabled
(RX4XE = 0). It is assumed that for binary bus frequencies the divided
down mux interface clock frequency will be 1.048576 MHz (t
bdlc
=
0.953674 µs). The symbol timing values are adjusted to compensate for
the shortening of the mux interface clock period.
Tables 112 and 113 show how the receive symbol timing values are
adjusted when 4X receive operation is enabled (RX4XE = 1) for both
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