Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Logic “1” A logic one is defined as either an active to passive transition followed
by a passive period 128µs in length, or a passive to active transition
followed by an active period 64µs in length (Figure 118(b)).
NB – Normalization
Bit
The NB symbol has the same property as a logic “1” or a logic “0”.It is
only used in IFR message responses.
SOF -– Start of
Frame Symbol
The SOF symbol is defined as passive to active transition followed by an
active period 200µs in length (Figure 118(c)). This allows the data bytes
which follow the SOF symbol to begin with a passive bit, regardless of
whether it is a logic one or a logic zero.
EOD – End of Data
Symbol
The EOD symbol is defined as an active to passive transition followed
by a passive period 200µs in length (Figure 118(d)).
EOF – End of
Frame Symbol
The EOF symbol is defined as an active to passive transition followed by
a passive period 280µs in length (Figure 118(e)). If there is no IFR byte
transmitted after an EOD symbol is transmitted, after another 80µs the
EOD becomes an EOF, indicating the completion of the message.
IFS – Inter-Frame
Separation
Symbol
The IFS symbol is defined as a passive period 300µs in length. The IFS
symbol contains no transition, since when used it always follows an EOF
symbol.
BREAK – Break
Signal
The BREAK signal is defined as a passive to active transition followed
by an active period of at least 240µs (Figure 118(f)).
IDLE An IDLE is defined as a passive period greater than 300µs in length.
J1850 VPW
Valid/Invalid Bits &
Symbols
The timing tolerances for receiving data bits and symbols from the J1850
bus have been defined to allow for variations in oscillator frequencies.In
many cases the maximum time allowed to define a data bit or symbol is
equal to the minimum time allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol
is being received is equal to a single period of the MUX Interface clock,
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Freescale Semiconductor, Inc.
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