Datasheet

Byte Data Link Controller Module
Functional Description
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Figure 118 J1850 VPW Symbols
Each message will begin with an SOF symbol, an active
symbol, and
therefore each data byte (including the CRC byte) will begin with a
passive
bit, regardless of whether it is a logic one or a logic zero. All
VPW bit lengths stated in the following descriptions are typical values at
a 10.4kbps bit rate.
Logic “0” A logic zero is defined as either an active to passive transition followed
by a passive period 64µs in length, or a passive to active transition
followed by an active period 128µs in length (Figure 118(a)).
128µs
Active
Passive
64µs
OR
Logic “0”
128µs
Active
Passive
64µs
OR
Logic “1”
200µs
Active
Passive
Start of Frame
200µs
End of Data
280µs
Active
Passive
End of Frame
≥ 240µs
Break
(a)
(b)
(c) (d)
(e) (f)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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