Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
A rising edge may occur during the IFS period because of varying clock
tolerances and loading of the J1850 bus, causing different nodes to
observe the completion of the IFS period at different times. Receivers
must synchronize to any SOF occurring during an IFS period to allow for
individual clock tolerances.
Break If the BDLC is transmitting at the time a BREAK is detected, it treats the
BREAK as if a transmission error had occurred, and halts
transmission.The BDLC cannot transmit a BREAK symbol. If while
receiving a message the BDLC detects a BREAK symbol, it treats the
BREAK as a reception error and sets the invalid symbol flag.If while
receiving a message in 4X mode, the BDLC detects a BREAK symbol,
it treats the BREAK as a reception error, sets BSVR register to $1C, and
exits 4X mode.The RX4XE bit in BCR2 is automatically cleared upon
reception of the BREAK symbol.
Idle Bus An idle condition exists on the bus during any passive period after
expiration of the IFS period. Any node sensing an idle bus condition can
begin transmission immediately.
J1850 VPW
Symbols
Variable Pulse Width modulation (VPW) is an encoding technique in
which each bit is defined by the time between successive transitions,
and by the level of the bus between transitions, active or passive. Active
and passive bits are used alternately. This encoding technique is used
to reduced the number of bus transitions for a given bit rate.
The symbol values shown below are nominal values. Refer to the
electrical specification for a more complete description of symbol values.
Each logic one or logic zero contains a single transition, and can be at
either the active or passive level and one of two lengths, either 64µs or
128µs (T
NOM
at 10.4kbps baud rate), depending upon the encoding of
the previous bit. The SOF, EOD, EOF and IFS symbols will always be
encoded at an assigned level and length. See Figure 118.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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