Datasheet

Pinout and Signal Description
Port Signals
MC9S12DP256 — Revision 1.1
Pinout and Signal Description
accumulator inputs. All eight pins are available for general-purpose I/O
when not configured for timer functions.
Port P for PWM The PWM module has a total of 8 external pins on which the pulse width
modulated waveforms are output. The 8 PWM outputs are multiplexed
on the PP[7:0] pins. This port is further shared with SPI 1 and 2 as well
as with interrupt inputs.
Port H Port H pins are used for interrupt inputs that can be used with pins
configured as inputs or outputs. The interrupts are triggered with either
the falling or the rising edge signal. An interrupt is generated if the
corresponding bit is enabled. There is an individual interrupt flag for
every pin.
Port J Port J pins 0, and 1 are used for interrupt inputs that can be used with
pins configured as inputs or outputs. The interrupts are triggered with
either the falling or the rising edge signal. An interrupt is generated if the
corresponding bit is enabled. There is an individual interrupt flag for
every pin. Port J pins 7 and 6 are shared amongst the 5th CAN module
and the bidirectional pins to IIC bus interface subsystem.
.
Table 8 MC9S12DP256 Port A, B, E, K Description Summary
Port Name
Pin
Numbers
Data Direction
Register
Description
112-pin
PE[7:0]
36 – 39
53 – 56
PE[1:0] In
PE[7:2] In/Out
DDRE
Mode selection, bus control signals and interrupt service
request signals; or general-purpose I/O.
PB[7:0] 31 – 24
In/Out
DDRB
Port A and port B pins are used for address and data in
expanded modes. The port data registers are not in the
address map during expanded and peripheral mode
operation. When in the map, port A and port B can be read or
written any time.
DDRA and DDRB are not in the address map in expanded or
peripheral modes.
PA[7:0] 64 – 57
In/Out
DDRA
PK[7, 5:0]
108, 19 –
20, 5 – 8
In/Out
DDRK
Expanded Address bits [19:14], and emulation chip select
signals or general-purpose I/O.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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