Datasheet

Byte Data Link Controller Module
Functional Description
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
The Data Latch will retain its value until the counter next reaches the
opposite end point, signifying a definite transition of the RxP signal.
Performance The performance of the digital filter is best described in the time domain
rather than the frequency domain.
If the signal on the RxP signal transitions, then there will be a delay
before that transition appears at the Filtered Rx Data output signal. This
delay will be between 15 and 16 clock periods, depending on where the
transition occurs with respect to the sampling points. This ‘filter delay’
must be taken into account when performing message arbitration.
For example, if the frequency of the MUX Interface clock (f
bdlc
) is
1.0486MHz, then the period (t
bdlc
) is 954ns and the maximum filter delay
in the absence of noise will be 15.259us.
The effect of random noise on the RxP signal depends on the
characteristics of the noise itself. Narrow noise pulses on the RxP signal
will be completely ignored if they are shorter than the filter delay. This
provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition
may be delayed by an amount equal to the length of the noise burst. This
is just a reflection of the uncertainty of where the transition is truly
occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the
shortest allowable symbol length will be detected by the next stage of the
BDLC’s receiver as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length
will normally be detected as an invalid symbol or as invalid data when
the frame’s CRC is checked.
J1850 Frame
Format
All messages transmitted on the J1850 bus are structured using the
format:
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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