Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Figure 116 BDLC Rx Digital Filter Block Diagram
Operation The clock for the digital filter is provided by the MUX Interface clock.At
each positive edge of the clock signal, the current state of the Receiver
input signal from the RxP pad is sampled.The RxP signal state is used
to determine whether the counter should increment or decrement at the
next positive edge of the clock signal.
The counter will increment if the input data sample is high but decrement
if the input sample is low.The counter will thus progress up towards ‘15’
if, on average, the RxP signal remains high or progress down towards ‘0’
if, on average, the RxP signal remains low.
When the counter eventually reaches the value ‘15’, the digital filter
decides that the condition of the RxP signal is at a stable logic level one
and the Data Latch is set, causing the Filtered Rx Data signal to become
a logic level one. Furthermore, the counter is prevented from overflowing
and can only be decremented from this state.
Alternatively, should the counter eventually reach the value ‘0’, the
digital filter decides that the condition of the RxP signal is at a stable logic
level zero and the Data Latch is reset, causing the Filtered Rx Data
signal to become a logic level zero. Furthermore, the counter is
prevented from underflowing and can only be incremented from this
state.
4-Bit Up/Down Counter
up/down out
dq
Filtered
Rx Data Out
MUX Interface Clock
Input
Sync
dq
Rx Data
from
RxP pad
4
Edge &
Count
Comparator
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