Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
General Purpose Input Ports
The input channel pins can be multiplexed between analog and digital
data. As analog inputs, they are multiplexed and sampled to supply
signals to the A/D converter. As digital inputs, they supply external input
data that can be accessed through the digital port registers. Each digital
input is individually enabled by each bit of the register ATDDIEN.
The analog/digital multiplex operation is performed in the input pads.
The input pad is always connected to the analog inputs of the ATD
module. The input pad signal is buffered before the data is bussed to the
digital port registers. The buffer is a schmitt trigger nand gate so that the
buffer can be turned off. This is important so that the buffer does not
draw excess current when analog potentials are presented at its input.
This is particularly important when some of the inputs are being used as
digital inputs and some as analog inputs. Analog signals present on the
input pins at the digital sampling time that don’t meet the V
IL
or V
IH
specification will return unknown digital values. A read of the PORTAD1
may affect the accuracy of an in progress sample period but will not
affect an in progress A/D conversion.
There is a digital, 8-bit, input-only port associated with the ATD. It is
accessed through the 8-bit Port Data Registers (PORTAD1). The
number of bits utilized in the port register depends on the number of
analog channels implemented with the 8 channel ATD module.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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