Datasheet

Analog to Digital Converter
Sample Conversion
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
clocks are disabled to most of the module and the analog quiescent
current draw is turned off; this places the module into its power down
state. This mode is equivalent to clearing the ADPU control bit in
ATDCTL2. The module is released from STOP mode when the
ipg_stop signal is released.
In this mode, the MCU still has access to the control, status, and result
registers.
IDLE Mode IDLE mode for the ATD module is defined as the state where the ATD
module is powered up and ready to perform an A/D conversion, but not
actually performing a conversion at the present time. Complete assess
to all control, status, and result registers is available. The module is
consuming near maximum power.
Sample Conversion
The sample/conversion time has three components: the initial sample
time, the final sample time, and resolution time. The initial sample time
is fixed at 2 ATD clock cycles. The final sample time is programmable
through control register ATDCTL 4 and can be 2, 4, 8, or 16 ATD clocks
cycles long. For a 10-bit conversion, the resolution time is 10 ATD clock
cycles.
Figure 112 illustrates how an ATD sample/conversion period is broken
into its various components for an 10-bit conversion with a
programmable sample time of 2 ATD clock cycles.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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