Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
determine when the result registers have been filled. The SCF bit is set
after the completion of each sequence. The CCF bit associated with
each result register is set when that register is loaded with result data.
1) Do not confuse conversion modes with MCU operating modes such as STOP, WAIT,
IDLE, RUN, DEBUG, and SPECIAL (test) modes, and do not confuse with module defined
operating modes such as power down, fast flag clear, 8-bit resolution, 10-bit resolution,
interrupt enable, clock prescaler setting, and freeze modes, and finally do not confuse with
module result data formats such as right justify mode, left justify mode, and
signed/unsigned data.
Special Operation Special mode is a device test mode. Special mode is entered when the
IP ipbi_test_mod signal is asserted. This mode allows increased
access to the control, status, and test registers. A number of special
mode test functions are also available.
Run Mode RUN mode for the ATD module is defined as the state where the ATD
module is powered up and currently performing an A/D conversion.
Complete assess to all control, status, and result registers is available.
The module is consuming maximum power.
Wait Mode WAIT mode is a maskable form of power saving.
WAIT mode is signalled to the ATD by asserting the ipg_wait signal on
the bus. If the AWAI control bit in ATDCTL2 is set, then the ATD
responds to WAIT mode. If the AWAI control bit is clear, then the ATD
ignores the ipg_wait signal. The ATD response to the wait mode is to
power down the module. The module is released from WAIT mode when
the ipg_wait signal is released.
In this mode, the MCU does
not
have access to the control, status, or
result registers.
Stop Mode STOP mode is a global mode that can be used to place the entire device
into power saving operation.
STOP mode is signalled to the ATD by asserting the ipg_stop signal.
This causes the ATD module to power down the ATD module. The digital
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Freescale Semiconductor, Inc.
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