Datasheet

Analog to Digital Converter
Modes of Operation
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
Modes of Operation
Analog to digital conversions in this module are performed in sequences.
There are a variety of different sequences that are programmable; these
different sequences are referred to as conversion modes
1
. A particular
conversion mode is defined by how many A/D conversions are
performed in a sequence, which analog input channels are examined
during a sequence, sample time length, whether sequences are
performed continuously or not, what event is used to trigger a
conversion, result register assignments, and so on.
The conversion modes for the ATD module are defined by the settings
of four control bits and three control values. The control bits are ETRIGE
in ATDCTL2 and MULT, SCAN and SC in ATDCTL5. In brief, ETRIGE
controls whether an external trigger is used to start a conversion
sequence. MULT controls whether the sequence examines a single
analog input channel or scans a number of different channels. SCAN
determines if sequences are performed continuously. SC determines if
we are performing a special conversion (i.e.: convert Vrl, Vrh,
(Vrl+Vrh)/2, usually used for test purposes). The control values are bits
CC/CB/CA in ATDCTL3/5 which define the input channels to be
examined; S8C/S1C in ATDCTL3/5 define the number of conversions in
a sequence; SMP0/SMP1 in ATDCTL4 define the length of the sample
time.
Sequences are initiated by writing to control registers 4 and 5. For the
continuous sequence modes, conversions will not stop until either
another non-continuous conversion sequence is initiated and finishes,
the ATD is powered down (ADPU control bit), the ATD is reset (by the
bus or the control bit), the bus ipg_wait line is activated (if the wait bit is
activated), or the bus ipg_stop line is activated. Note that the ipg_wait
signal suspends the current conversion until the ipg_wait is deactivated
- it does not terminate the conversion. The result of suspended
conversion is not guaranteed.
The MCU can use one of two methods to learn when the result data is
available in the result registers. First, the interrupt enable bit can be used
to interrupt the MCU when the sequence is complete. Second, the
conversion complete flags can be used to poll the ATD module to
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