Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
this selection is made using the DSGN control bit in ATDCTL2. Note that
the signed data is stored in 2s complement format. Note that signed data
only exists in left justified format so that no sign extension hardware is
required. Signed data selected for right justified format is ignored.
For 8-bit result data, the result data maps between the high (left justified)
and low (right justified) order bytes of the result register. For 10-bit result
data, the result data maps between bits 6–15 (left justified) and bits 0–9
(right justified) of the result register. Therefore for each bit in the SAR,
there are 3 possible mappings of this bit into the result registers.
These registers are normally read-only. In special (test) mode the result
registers can be written.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...