Datasheet

Analog to Digital Converter
Register Descriptions
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
ATDDRx A/D
Conversion Result
Registers
(ATDDR0Ð15)
Left Justified Result Data
Right Justified Result Data
x = 0, 1, 2, 3, 4, 5, 6, 7
The A/D conversion results are stored in 8 result registers. These
registers are designated ATDDR0 through ATDDR7. The number of
result registers in a particular version of the ATD module equals the
number of analog input channels.
The result data is formatted in the result registers based on two criteria.
First there is left and right justification; this selection is made using the
DJM control bit in ATDCTL2. Second there is signed and unsigned data;
Address Offset: $_01(2x)
ATDDRxH Bit 15 14 13 12 11 10 9 Bit 8
10-bit data
8-bit data
Bit 9 MSB
Bit 7 MSB
Bit 8
Bit 6
Bit 7
Bit 5
Bit 6
Bit 4
Bit 5
Bit 3
Bit 4
Bit 2
Bit 3
Bit 1
Bit 2
Bit 0
RESET
UUUUUUUU
Address Offset: $_01(2x+1)
ATDDRxL Bit 7 654321Bit 0
10-bit data
8-bit data
Bit 1
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
UUUUUUUU
Address Offset: $_01(2x)
ATDDRxH Bit 15 14 13 12 11 10 9 Bit 8
10-bit data
8-bit data
0
0
0
0
0
0
0
0
0
0
0
0
Bit 9 MSB
0
Bit 8
0
RESET
UUUUUUUU
Address Offset: $_01(2x+1)
ATDDRxL Bit 7 654321Bit 0
10-bit data
8-bit data
Bit 7
Bit 7 MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
RESET
UUUUUUUU
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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