Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
Port Data Register
(PORTAD1)
The input data port associated with the ATD module is input-only. The
port pins are shared with the analog A/D inputs.
Reset: Reading this register out of reset will result in a “1” unless the pin
was enabled by setting the respective bit in the ATDDIEN register, which
is cleared out of reset.
The ATD input ports may be used for general purpose digital input.
When the port data registers are read, they contain the digital levels
appearing on the input pins at the time of the read. Input pins with signal
potentials not meeting V
IL
or V
IH
specifications will have an
indeterminate value.
Use of any Port pin for digital input does not preclude the use of any
other Port pin for analog input. Note that the digital/analog multiplexing
function is performed in the input pad. The port registers are connected
to the input pads through a tristate buffers. These buffers are only
activated when a read to a port register is performed so that analog
signal potentials on the input pins will not cause the buffers to draw
excess supply current.
Writes to this register have no meaning at any time.
Address Offset: $000F
Bit 7 654321Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin Function
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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