Datasheet

Analog to Digital Converter
Register Descriptions
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
ATD TEST Module
Test Register
(ATDTEST)
The test registers implement various special (test) modes used to test
the ATD module. The reset bit in ATDTEST1 is always read/write. The
SAR (successive approximation register) can always be read but only
written in special (test) mode.
When writing to the SAR in special (test) mode, it is advised to use 16
bit write. Using an 8-bit write to ATDTEST0 will corrupt the SAR[1:0]
(ATDTEST1 [7:6]) bits. This is a known bug.
The functions implemented by the test registers are reserved for factory
test.
SAR 9–0 — Successive Approximation Register
This ten bit value represents the contents of the AD machine’s
successive approximation register. This value can always be read. It
can only be written in special (test) mode. Note that ATDTEST0 acts
as a ten bit register since the entire SAR is read/written when
accessing this address.
RST — Test Mode Reset Bit
1 = Reset the ATD module.
0 = No reset.
When set, this bit causes the ATD module to reset itself. This resets
all registers to their reset state (note the system reset state of the
reset bit is zero), with the exception of the ADPU bit and itself. This
also aborts the current conversion and conversion sequence, clears
all pending interrupts, and puts the module in an idle mode.
Address Offset: $0008–$0009
Bit 15 14 13 12 11 10 9 Bit 8
SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2
Reset: 10000000
Bit 7 654321Bit 0
SAR1 SAR0 0 0 0 RST ATDCLK SC
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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