Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
A/D Status Register
(ATDSTAT)
The ATD Status registers contain the conversion complete flags and the
conversion sequence counter. The status registers are normally
read-only. In special (test) mode, the SCF bit and the CCF bits may also
be written.
SCF — Sequence Complete Flag
This flag is set upon completion of a conversion sequence. If
conversion sequences are continuously performed (SCAN=1), the
flag is set after each one is completed. How this flag is cleared
depends on the setting of the fast flag clear bit (AFFC in ATDCTL2).
When AFFC=0, SCF is cleared when a new conversion sequence is
initiated (write to register ATDCTL4/5). When AFFC=1, SCF is
cleared after reading the first (any) result register.
Table 105 Analog Input Channel Select Coding
CC CB CA
Analog Input
Channel
000 AD0
001 AD1
010 AD2
011 AD3
100 AD4
101 AD5
110 AD6
111 AD7
Address Offset: $0006–$0007
Bit 15 14 13 12 11 10 9 Bit 8
SCF 0 ETORF FIFOR 0 CC2 CC1 CC0
Reset: 00000000
Bit 7 654321Bit 0
CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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