Datasheet

Table Of Contents
Analog to Digital Converter
Register Descriptions
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
If this control bit is 1, a single conversion sequence initiation will result
in continuously executed conversion sequence. When a conversion
sequence completes, the sequence complete flag (SCF) is set and a
new sequence is immediately begun. The conversion mode
characteristics of each sequence are identical. If a new conversion
mode is required, the existing continuous sequence must be
interrupted, the control registers modified, and a new conversion
sequence initiated.
MULT — Multi-Channel Sample Mode
1 = Sample across many channels.
0 = Sample only the specified channel.
When MULT is 0, the ATD sequence controller samples only from the
specified analog input channel for an entire conversion sequence.
The analog channel is selected by channel selection code (control
bits CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD
sequence controller samples across channels. The number of
channels sampled is determined by the sequence length value (S8C,
S1C control bits). The first analog channel examined is determined by
channel selection code (CC, CB, CA control bits); subsequent
channels sampled in the sequence are determined by incrementing
the channel selection code.
CC, CB, CA — Analog Input Channel Select Code
These bits select the analog input channel(s) whose signals are
sampled and converted to digital codes. Table 105 lists the coding
used to select the various analog input channels. In the case of single
channel scans (MULT=0), this selection code specified the channel
examined. In the case of multi-channel scans (MULT=1), this
selection code represents the first channel to be examined in the
conversion sequence. Subsequent channels are determined by
incrementing channel selection code; selection codes that reach the
maximum value wrap around to the minimum value.
Note that for special conversion mode, bits CC/CB/CA have a
different function. Instead of specifying the analog input channel, they
identify which special channel conversion is to take place. See
Table 106 for a list of the special conversions that are available
through these bits.
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