Datasheet

Analog to Digital Converter
Register Descriptions
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
sequence is aborted. A write to this register (or ATDCTL4) initiates a
new conversion sequence.
DJM — Result Register Data Justification Mode
1 = Right justified mode.
0 = Left justified mode.
This bit determines how the result register data maps onto the IP data
bus bits. The mapping depends on resolution setting of the A/D
converter.
For 10-bit resolution, left justified mode maps a result register into
data bus bits 6 through 15; bit 15 is the MSB. In right justified mode,
the result registers maps onto data bus bits 0 through 9; bit 9 is the
MSB.
For 8-bit resolution, left justified mode maps a result into the high byte
(bits 8 though 15; bit 15 is the MSB). Right justified maps a result into
the low byte (bits 0 through 7; bit 7 is the MSB).
The IP bus signal sz8 forces all data transfers to be 8-bits wide. This
does not affect the justification of the data. Only the byte addressed
is retrieved.
DSGN — Signed/Unsigned Result Data Mode
1 = Signed result register data select.
0 = Unsigned result register data select.
The signed/unsigned result data control bit determined is the result
data read from the result registers is signed data or unsigned data.
Signed data is represented as 2’s complement data.
Note that signed data is not available for right justified data.
Therefore, sign extension hardware is not required.
Table 103 summarizes the result data formats available and how they
are set up using the control bits.
Address Offset: $0005
Bit 7 654321Bit 0
DJM DSGN SCAN MULT 0 CC CB CA
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...