Datasheet

Analog to Digital Converter
Register Descriptions
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
external analog signal directly to the storage node for final charging
and high accuracy. Table 101 lists the lengths available for the third
sample phase.
PRS0, PRS1, PRS2, PRS3, PRS4 — ATD Clock Prescaler
The binary prescaler value (0 to 31) plus one (1 to 32) becomes the
divide-by factor for a modulus counter used to prescale the ATD
module clock frequency. The resulting scaled clock is further divided
by 2 before the ATD conversion clock is generated. This clock is used
to drive the S/H and A/D machines.
Note that the maximum ATD conversion clock frequency is half of the
ATD module clock. The default prescaler value is one which results in
a default ATD conversion clock frequency that is quarter of the ATD
module clock. Table 102 illustrates the divide-by operation and the
appropriate range of ATD module clock frequencies.
Table 101 Sample Time Select
SMP1 SMP0 Final Sample Time
0
0
1
1
0
1
0
1
2 A/D clock periods
4 A/D clock periods
8 A/D clock periods
16 A/D clock periods
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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