Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
ATD Control
Register 4
(ATDCTL4)
ATD control register 4 is used to select the ATD conversion clock
frequency (based on the ATD module clock), select the length of the
third phase of the sample period, and set the resolution of the A/D
conversion (i.e.: 8-bits or 10-bits). All writes to this register have an
immediate effect. If a conversion is in progress, the entire conversion
sequence is aborted.
SRES8 — A/D Resolution Select
1 = 8-bit resolution selected.
0 = 10-bit resolution selected.
This bit determines the resolution of the A/D converter: 8-bits or
10-bits. The A/D converter has the accuracy of a 10-bit converter.
However, if low resolution is required, the conversion can be speeded
up by selecting 8-bit resolution.
SMP0, SMP1 — Sample Time Select
These two bits select the length of the third phase of the sample
period in ATD conversion clock cycles. Note that the ATD conversion
clock period is itself a function of the prescaler value (bits PRS0-4).
The sample period consists of three phases. The first phase is two
ATD conversion clock cycles long and samples the signal on the
channel’s sample capacitor. The second phase is four clock cycles
and its purpose is to quickly transfer the sample onto the A/D
machine’s storage node in preparation for conversion. The third
phase occurs after the buffered sample and transfer and attaches the
Address Offset: $0004
Bit 15 14 13 12 11 10 9 Bit 8
SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
Reset: 00000101
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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