Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Pinout and Signal Description
MC9S12DP256 — Revision 1.1
Pinout and Signal Description
Port Signals
The MC9S12DP256 incorporates eleven ports which are used to control
and access the various device subsystems. When not used for these
purposes, port pins may be used for general-purpose I/O. In addition to
the pins described below, each port consists of a data register which can
be read and written at any time, and, with the exception of port AD0, port
AD1, and PE[1:0] a data direction register which controls the direction of
each pin. After reset all general purpose I/O pins are configured as input.
Port A Port A bits 7 through 0 are associated with address lines A15 through A8
respectively and data lines D15/D7 through D8/D0 respectively. When
this port is not used for external addresses such as in single-chip mode,
these pins can be used as general purpose I/O. Data Direction Register
A (DDRA) determines the primary direction of each pin. DDRA also
determines the source of data for a read of PORTA.
Register DDRA determines whether each port A pin is an input or output.
DDRA is not in the address map during expanded and peripheral mode
operation. Setting a bit in DDRA makes the corresponding bit in port A
an output; clearing a bit in DDRA makes the corresponding bit in port A
an input. The default reset state of DDRA is all zeroes.
This register is not in the on-chip map in expanded and peripheral
modes.
Port B Port B bits 7 through 0 are associated with address lines A7 through A0
respectively and data lines D7 through D0 respectively. When this port
is not used for external addresses, such as in single-chip mode, these
pins can be used as general purpose I/O. Data Direction Register B
(DDRB) determines the primary direction of each pin. DDRB also
determines the source of data for a read of PORTB.
Register DDRB determines whether each port B pin is an input or output.
DDRB is not in the address map during expanded and peripheral mode
operation. Setting a bit in DDRB makes the corresponding bit in port B
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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