Datasheet

Analog to Digital Converter
Register Descriptions
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
conversion counter value in ATDSTAT0 can be used to determine
where in the result register file, the next conversion result will be
placed.
The results register counter is initialized to zero on three events: on
reset, the beginning of a normal (non-FIFO) conversion sequence,
and the end of a normal (non-FIFO) conversion sequence. Therefore,
the reset bit in register ATDTEST1 can be toggled to zero the result
register counter; any sequence allowed to complete normally will zero
the result register counter; a new sequence (non-FIFO) initiated with
a write to ATDCTL4/5 followed by a write to ATDCTL3 to set the FIFO
bit will start a FIFO sequence with the result register initialized.
Finally, which result registers hold valid data can be tracked using the
conversion complete flags. Fast flag clear mode may or may not be
useful in a particular application to track valid data.
FRZ1, FRZ0 — Background Debug Freeze Enable
Background debug freeze function allows the ATD module to pause
when a breakpoint is encountered. A breakpoint is signaled when the
IP bus asserts the ipg_freeze signal. Table 100 shows how FRZ1 and
FRZ0 determine the ATD’s response to a breakpoint. When the
ipg_freeze signal is released, the ATD module continues operating as
it was before the breakpoint occurred. The module is
not reset; the
register file is
not initialized; the conversion sequence is not restarted
(i.e.: current sequence is aborted and a new one started).
Table 100 Module Freeze Response
FRZ1 FRZ0 ATD RESPONSE
0
0
1
1
0
1
0
1
Ignore the background signal
Reserved
Finish current conversion, then freeze
Freeze Immediately
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...