Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
The result register assignments made to a conversion sequence
follow a few simple rules. Normally, the first result is placed in the first
register; the second result is placed in the second register, and so on.
Table 99 presents the result register assignments for the various
conversion lengths that are normally made. If FIFO mode is used, the
result register assignments differ. The results are placed in
consecutive registers between conversion sequences; the result
register mapping wraps around when the end of the register file is
reached.
FIFO — Result Register FIFO Mode
1 = Result registers do not map to the conversion sequence.
0 = Result registers maps to the conversion sequence.
In normal operation, the A/D conversion results map into the result
registers based on the conversion sequence; the result of the first
conversion appears in the first result register, the second result in the
second result register, and so on. In FIFO mode the result register
counter is not reset at the beginning or ending of a conversion
sequence; conversion results are placed in consecutive result
registers between sequences. The result register counter wraps
around when it reaches the end of the result register file. The
Table 99 Result Register Assignment for Different Conversion
Sequences.
Number of Conversions
per Sequence
Result Register
Assignment
1 ATDDR0
2 ATDDR0 through ATDDR1
3 ATDDR0 through ATDDR2
4 ATDDR0 through ATDDR3
5 ATDDR0 through ATDDR4
6 ATDDR0 through ATDDR5
7 ATDDR0 through ATDDR6
8 ATDDR0 through ATDDR7
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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