Datasheet

Analog to Digital Converter
Register Descriptions
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
The sequence complete interrupt flag. This flag is not cleared until the
interrupt is serviced (by reading the result data in such a way that the
conversion complete flag is cleared), a new conversion sequence is
initiated, or the module is reset. This bit is not writable in any mode.
S8C/S4C/S2C/S1C — Conversion Sequence Length
S8C/S4C/S2C/S1C represents a binary value which is the length of
the conversion sequence. Table 98 lists the coding combinations
implemented.
At reset, S4C is set to 1, so that the sequence length is 4 after reset.
This is to maintain software continuity to HC12 familiy. In other HC12
designs, the reset state for the SxCs are 0, which defaults to a
sequence length of four.
Note that the maximum number of conversions in a sequence
depends on how many channels are available in the ATD module.
This module is an 8 channel module. The number of result registers
is also 8. Each A/D conversion result is stored in one result register.
Therefore the maximum number of conversions in a sequence is
limited to the number of result registers in the module. In this case, the
maximum number of conversions is 8; therefore, at 0000, the number
of conversions is 8.
Table 98 Conversion Sequence Length Coding.
S8C S4C S2C S1C
Number of Conversions per
Sequence
0000 8
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1XXX 8
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