Datasheet

Analog to Digital Converter
Register Descriptions
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
conversion sequence is begun by writing to control register
ATDCTL4/5. In application where the ATD module is being polled to
determine if an ATD conversion is complete, this feature provides a
convenient way of clearing the status register conversion complete
flag.
In applications where ATD interrupts are used to signal conversion
completion, the precondition of reading the status register can be
eliminated – hence the fast conversion complete flag clear mode. In
this mode, any access to a result register will cause its associated
conversion complete flag in the status register to be cleared. The SCF
flag is cleared after the first (any) result register is read.
AWAI — ATD Wait Mode
1 = Enable ATD wait function during MCU Wait mode.
0 = Disable ATD wait function.
The wait function allows the MCU to selectively halt and power down
the ATD module. If the AWAI bit is set and the MCU asserts the IP bus
wait_mode, then the ATD module immediately halts operation and
powers down. When the wait_mode is released, the ATD module
powers up and continues operation. The module is
not reset; the
register file is
not initialized; the conversion sequence is not restarted.
If the AWAI is reset (zero), then the ATD module ignores the
wait_mode line.
ETRIGLE — External Trigger Level/Edge control
This bit sets the mode of the incoming external trigger signal
1 = Level mode – active level gates ATD operation
0 = Edge mode – active edge mode
ETRIGP — External Trigger Polarity
This bit controls the polarity of the external trigger signal
1 = Active high level or rising edge active
0 = Active low level or falling edge active
ETRIGE — External Trigger Mode enable
1 = Enable external trigger mode
0 = Disable external trigger mode.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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