Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
ATD Control
Register 2 & 3
(ATDCTL2,
ATDCTL3)
The ATD control register 2 & 3 are used to select the power up mode,
fast flag clear mode, wait mode, 1 to 8 channel mode, interrupt control,
and freeze control. Writes to these registers will
not abort current
conversion sequence
nor start a new sequence.
READ: any time
WRITE: any time
(except for Bit 8 – ASCIF, READ: any time, WRITE: not allowed)
Bit Positions: 7
This bit is unused and always reads back as zero
ADPU — ATD Disable / Power Down
1 = Normal ATD functionality.
0 = Disable and power down the ATD.
This bit provides program on/off control over the ATD module allowing
reduced MCU power consumption when the ATD is not being used.
When reset to zero, the ADPU bit aborts any conversion sequence in
progress. Because the analog electronics is turned off when
powered down, the ATD requires a recovery time period when ADPU
bit is enabled.
AFFC — ATD Fast Conversion Complete Flag Clear
1 = All ATD conversion complete flags use fast clear mode.
0 = All ATD conversion complete flags clear normally.
Normal conversion complete clearing means that the status register
must be read after the conversion complete flag has been set before
that flag can be reset. After the status register read, a read to the
associated result register causes its conversion complete flag in the
status register to be cleared. The SCF flag is cleared when a new
Address Offset: $0002–$0003
Bit 15 14 13 12 11 10 9 Bit 8
ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF
Reset: 00000000
Bit 7 654321Bit 0
0 S8C S4C S2C S1C FIFO FRZ1 FRZ0
Reset: 00100000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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