Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
Register Descriptions
Register
Arrangement and
IP Address
Mapping
The base address of the module is hardware programmable. The ATD
register map is fixed and begins at the module’s base address.
Figure 111 summarizes the ATD module’s address space. The following
subsections describe the bit-level arrangement and functionality of each
register.
The ATD module is clocked by the ATD module clock. The module
signals valid output data to the MCU via interrupts or conversion
complete flags. Therefore, it does not need a synchronizing signal to
inform the CPU of conversion complete.
The module has two internal buses with which to move control, status,
and result data between internal registers and the IP bus. The IP bus
controls activity on these internal buses based on bus requests to the
ATD module. The ATD module moves result data into the dual ported
result registers through a separate dedicated result bus to avoid
collisions with IP bus accesses. Special attention is paid so that IP bus
accesses to the ATD register file do not conflict with module updates to
the same register at the same time.
When control bits are written by the IP bus, they update the control
register immediately. If an A/D conversion is in progress, the results are
not guaranteed until the next A/D conversion cycle begins.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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