Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
Background
Debug (ATD
FREEZE) Mode
When debugging an application, it is useful to have the ATD pause when
a breakpoint is encountered. To accommodate this, there are two
FREEZE bits in the ATDCTL3 register used to select one of three
responses: First, the ATD module may ignore the background signal.
Second, it may respond to the freeze request by finishing the current
conversion and freezing before starting the next sample period. Third, it
may respond by immediately freezing.
The FREEZE state is implemented by stopping the ATD clock when the
module background signal is asserted. Control and timing logic is static
allowing the register contents and timing position to be remembered
indefinitely. The analog electronics remains powered up; however,
leakage onto the storage node and comparator reference capacitors
may compromise the accuracy of a frozen conversion depending on the
length of the freeze period. When the background signal is negated,
clock activity resumes. The bus interface remains active to allow module
access to the ATD register block during the frozen period.
Module Reset The ATD module is reset on two different events. First, if the IP bus
master reset signal is activated, the ATD module is reset. Second, if the
RST bit in the ATDTEST register is activated, the ATD module is reset.
The single difference between the two events is that the RST bit event
does not reset the ADPU bit to its reset state value - i.e.: the module is
not reset into a powered down state.
The ATD module reset function places the module back into an
initialized state. If the module is performing a conversion sequence,
both the current conversion and the sequence are terminated. The
conversion complete flags are cleared and any pending interrupts are
cancelled. Note that the control, test, and status registers are initialized
on reset; the initialized register state is defined in the register description
section of this specification.
The ATD module is powered down on reset (except for the RST bit reset
event). This occurs as a function of the register file initialization; the reset
definition of the ADPU bit (power down bit) is zero or powered down.
Note the RST bit reset event does not reset the ADPU bit to its reset
value so the module will be returned to an idle state following this reset
triggering event.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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