Datasheet

Analog to Digital Converter
Functional Description
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
Figure 109 ATD Clock Select/Prescale.
Power Down Mode The ATD module can be powered down under program control. This is
done by turning the clock signals off to the digital electronics of the
module and eliminating the quiescent current draw of the analog
electronics.
Program power down control is implemented in one of three ways. First,
by using the ADPU bit in control register ATDCTL2, the module can be
powered down when this bit is reset to zero. Second, when the module
bus ipg_stop is activated, the module will power down for the duration
of the ipg_stop signal. Third, if the module stop_in_wait enable bit is set
and the ipg_wait line is activated, the module will power down for the
duration of the ipg_wait signal.
Note that the reset default for the ADPU bit is zero. Therefore, when this
module is reset, it is reset into the power down state. (The exception is
the test mode power down which resets the module into idle mode.)
Once the command to power down has been received, the ATD module
aborts any conversion sequence in progress and enters lower power
mode. When the module is powered up again, the module must be
given time to stabilize the bias settings in the analog electronics before
conversions can be performed. Note that powering up the module does
not reset the module since the register file is not initialized.
Note that in power down mode, the control and result registers are still
accessible.
Modulus Counter
DIVIDE
BY 2
PR0–PR4
ATD Conversion CLOCK
ATD Module Clock
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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