Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
During a conversion, if additional active edges are detected, an overrun
error condition exists. If one or more edges are detected during a
conversion sequence, the overrun flag is set; ETORF bit in ATDSTAT0.
In level trigger mode, the active level of the external trigger signal is used
to gate the ATD module. The ATD conversion is performed immediately
after the sample period is completed. At the end of conversion
sequence, if the active level is still present the sample and conversion
process is performed again.
In either level or edge triggered modes, the first conversion begins when
the trigger is received. In both cases, the maximum latency time for the
ATD module is 1 ATD module clock cycle plus any skew or delay
introduced by the trigger circuitry.
NOTE: Note that if the ETRIG input shares an analog channel input any ATD
conversions performed on samples from the external trigger channel will
be erroneous while the external trigger mode is enabled
.
Table 96 External Trigger Control Bits
ETRIGLE ETRIGP ETRIGE SCAN Description
XX00
Ignores external trigger. Performs
one conversion sequence and
stops.
XX01
Ignores external trigger. Performs
continuous conversion
sequences.
001X
Falling edge triggered. Performs
one conversion sequence per
trigger.
011X
Rising edge triggered. Performs
one conversion sequence per
trigger.
101X
Trigger active low. Performs
continuous conversions while
trigger is active.
111X
Trigger active high. Performs
continuous conversions while
trigger is active.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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