Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
A/D State
Machine and SAR
(Successive
Approximation
Register)
The A/D state machine controls the conversion process in the A/D
converter. The machine needs to know when a sample period is
occurring since the sample storage node is located on the CDAC
capacitor array. The machine works closely with the SAR to perform a
binary search algorithm. The intermediate results in the SAR are used
by the CDAC and RDAC interface circuits to determine which switches
to set to generate the next approximation potential. At the end of the
conversion process, the SAR contains the nearest approximation to the
sampled signal given the resolution of the A/D converter.
Limitations The specification minimum conversion time is set by the settling time of
the digitally generated compare potentials. The settling time is limited by
the RC time constant of the RDAC/CDAC arrays. Basically it takes 2
clocks to settle. So the time constant is approximately 1
µsec.
Conversion Mode
Control and
Register File
This section defines the programmer interface to the ATD module. The
register file defines the address space used to access the module’s
controls, status, and data. The conversion mode control uses the control
register settings to define the overall flow of the ATD module’s
operations.
Control/Status
Registers and
Control Section
There are eight control registers and three status registers associated
with the ATD module. IP bus writes to ATDCTL4&5 registers initiate a
new conversion sequence. If a conversion sequence is already running,
this sequence will be aborted and a new sequence will be begun.
The Mode Control communicates with the S/H machine and the A/D
machine when necessary to collect samples and perform conversions.
The Mode Control issues a “begin_sample” signal which for a normal
conversion signals the S/H machine to begin collecting a sample and for
the A/D machine to begin receiving a sample. At the end of the sample
period, the S/H machine issues a end_sample signal which signals the
A/D machine to begin the analog to digital conversion process. The
conversion process is terminated when the A/D machine issues an
end_convert signal back to the Mode Control unit. For special test mode
conversions (V
RL
, V
RH
, (V
RL
+V
RH
)/2), the sample machine is important
because it generates an end_sample signal; the A/D machine uses the
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