Datasheet

Analog to Digital Converter
Functional Description
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
When not sampling, the analog-to-digital submodule disables its own
clocks at the input into this submodule. The analog electronics still draws
quiescent current. The power down (ADPU) bit must be set to disable
both the digital clocks and the analog power consumption.
Note that only analog input signals within the potential range of V
RL
to
V
RH
(A/D reference potentials) will result in a non-railed digital output
codes.
This sub-module performs special test conversions internally without the
aid of the sample submodule (i.e.: to convert V
RL
, V
RH
, and
(V
RL
+V
RH
)/2).
Resistor and
Capacitor DAC
Arrays
The A/D core is a 10 bit analog to digital converter implemented in a
0.25 micron CMOS process capable of being manufactured in numer-
ous foundries without detrimental affects. It must also be capable of
accepting 5 volts inputs without permanent damage while simulta-
neously operating at 5 volts. This can be rather challenging.
The heart of the converter consist of a combination of resistors and
capacitors. In particular, a thermometer code 7 bit resistor string for the
MSB and 3 bits of capacitors to determine the LSB. The chip presently
operates with a single-ended signal but can be modified for a sign bit
which would allow for negative signals.
The design is a 10 bit single ended design using a “pseudo” differential
scheme. The first 7 MSB bits consist of a 1 of 128 resistor string. The
remaining 3 LSB bits are binary weighted capacitor of value 8c, 4c, 2c,
and 1c. The last C is an extra C which can be used for offset
compensation of + 1/2 LSB.
Comparator The comparator is a three stage comparator. The first two stages are
capacitively coupled, differential comparator stages; these add a fixed
gain to the comparison signal. The last stage is a clocked regenerative
comparator stage; this stage drives the input comparison signal to the
operating potential rails. The input offset voltage of the comparator is
removed from the stored sample by zeroing the comparator before the
sample process. The gain required by the comparator for 10-bit
accuracy is greater than 60dB.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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