Datasheet

Analog to Digital Converter
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
The analog input multiplexer includes negative stress protection circuitry
which prevents crosstalk between channels when the applied input
potentials are within specification.
Sample Buffer
Amplifier
The sample amplifier is used to buffer the input analog signal so that the
storage node can be quickly charged to the sample potential.
Limitations The current ATD module architecture allows for only one sample storage
node which is located in the A/D machine. As a result, only one sample
can be held at a time; this means the S/H machine and the A/D machine
cannot run concurrently even though they are independent machines.
The minimum conversion time is therefore dependent on the program
selection of the sample time. The current minimum conversion time
specification uses the minimum sample time.
No DC level correction, channel to channel gain adjust, or other data
acquisition functions are currently performed on the input analog signals.
Analog-to-Digital
Converter
Submodule
The Analog-to-Digital (A/D) Machine performs analog to digital
conversions. The resolution of the A/D converter is program selectable
at either 8 or 10 bits. This machine uses a successive approximation A/D
architecture. It functions by comparing the stored analog sample
potential with a series of digitally generated analog potentials. By
following a binary search algorithm, the converter locates the
approximating potential that is nearest to the sampled potential.
This submodule contains all the necessary analog and digital electronics
to perform a single analog to digital conversion. This module accepts as
input a begin_sample signal, an end_sample signal, a 8/10 bit resolution
select line, a special conversion select line, a two wire conversion type
bus, a reset signal, a power down signal, a clock signal, an input analog
signal, and two reference potentials. This submodule provides as output
a 10-bit digital word and an end_convert signal as outputs. For power,
this submodule requires VDD, VDDA, VSS, VSSA. and Vhv (the
in-module generated high voltage potential). One bias line is required
from the bias generator.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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