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Analog to Digital Converter
Functional Description
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
Functional Description
Please refer to the functional block diagram Figure 108 in reference to
the functional description of the ATD module
Custom Analog
Sample and Hold
Submodule
The Sample and Hold (S/H) Machine accepts analog signals from the
external world and stores them as capacitor charge on a storage node
in the module. With the exception of the storage node, this sub-module
contains all analog and digital electronics required to perform a single
sample. The current sample process uses a stage approach. During the
stage, the sample amplifier is used to quickly charge the storage node
with a reflection of the sample capacitor potential. The final stage
connects the input directly to the storage node to complete the sample
for high accuracy.
This submodule accepts as input a begin_sample signal, a sample time
code, a channel select code, a reset signal, a power down signal, two
clock signals, and 8 analog lines. This submodule provides as output an
end_sample signal and an analog sampled signal (during the sample
period). For power, this submodule requires VDD, VDDA, VSS, and
VSSA. Two bias lines are required from the bias generator.
When not sampling, the sample and hold submodule disables its own
clocks at the input into this submodule. The analog electronics still draw
their quiescent current. The power down (ADPU) bit must be set to
disable both the digital clocks and the analog power consumption.
The input analog signals are unipolar. The signals must fall within the
potential range of VSSA to VDDA (analog electronics supply potentials).
This sub-module is not required in order to perform the special
conversions (i.e.: to convert Vrl, Vrh, and (Vrl+Vrh)/2).
Analog Input
Multiplexer
The analog input multiplexer selects one of the 8 external analog input
channels to generate an analog sample. It can be expanded to 16
external analog input channels.
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