Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 80 (14x14) 16-Bit 25 MHz I/O number 59

Table Of Contents

List of Sections
Table of Contents
General Description
- Contents
- Introduction
- Features
- MC9S12DP256 112-Pin Block Diagram
- Ordering Information
Central Processing Unit (CPU)
- Contents
- Introduction
- Programming Model
- Data Types
- Addressing Modes
- Indexed Addressing Modes
- Opcodes and Operands
- Instruction Set Summary
Pinout and Signal Description
- Contents
- MC9S12DP256 Pin Assignments in 112-pin QFP
- Power Supply Pins
- Signal Descriptions
- Port Signals
System Configuration
- Contents
- Introduction
- Modules Variabilities
- MCU Variabilities
Registers
- Contents
- Register Block
Operating Modes
- Contents
- Introduction
- Operating Modes
- Background Debug Mode
- Security
Resource Mapping
- Contents
- Introduction
- Internal Resource Mapping
- Flash EEPROM mapping through internal Memory Expansion
- Miscellaneous System Control Register
- Memory Maps
Bus Control and Input/Output
- Contents
- Introduction
- Detecting Access Type from External Signals
- Stretched Bus Cycles
- PIPE Status Signals
- Registers
Resets and Interrupts
- Contents
- Introduction
- Register Map
- Exception Priority
- Maskable interrupts
- Latching of Interrupts
- Register Descriptions
- Resets
- Effects of Reset
- Register Stacking
Voltage Regulator (VREG)
- Contents
- Overview
- Features
- Block Diagram
- Functional Description
- External Pin Connection
- Reset Initialization
- Modes of Operation
Flash EEPROM 256K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
EEPROM 4K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Interrupt Operation
Port Integration Module
- Contents
- Overview
- Block Diagram
- External Pin Descriptions
- 80 Pin QFP bond-out version
- Register Map
- Register Descriptions
- Reset Initialization
- Functional Description
- Low Power Options
- Interrupt Operation
Clocks and Reset Generator (CRG)
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Interrupt Operation
- Low Power Options
Pulse Width Modulator (PWM)
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Register Descriptions
- Functional Description
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
Enhanced Capture Timer (ECT)
- Contents
- Overview
- Features
- Modes of Operation
- Abbreviations
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Modes of Operation
- Interrupts
- Description of Interrupt Operation
Serial Communications Interface (SCI)
- Contents
- Overview
- Features
- Modes of Operation
- SCI Interface Diagram
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Modes of Operation
- Interrupt Operation
Serial Peripheral Interface (SPI)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Low Power Mode Options
- Errata
- Reset
- Interrupts
Inter-IC Bus (IIC)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- I-Bus Protocol
- Interrupt Operation
- Modes of Operation
- Programming
MSCAN
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Functional Description
- Register Descriptions
- Modes of Operation
- Low Power Options
- Interrupt Operation
Analog to Digital Converter
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Sample Conversion
- General Purpose Input Ports
Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
Background Debug Module (BDM)
- Contents
- Overview
- Interface Signals
- Registers
- Operation
- Modes of Operation
- Low-Power Options
- Interrupt Operation
Breakpoint (BKP) Module
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Descriptions
- Functional Description
- Breakpoint Operating Modes
- Breakpoint Types
- Modes of Operation
- Low Power Options
- Reset Initialization
- Interrupt Operation
- General Purpose I/O Ports
Revision History
- Changes from Rev 1.0 to Rev 1.1
Glossary
Literature Updates
- Literature Distribution Centers
- Customer Focus Center
- Microcontroller Division’s Web Site

Pinout and Signal Description

MC9S12DP256 — Revision 1.1

Pinout and Signal Description

AN05 PAD05 VDDA 77 A/D Converter 0 channel 5

AN13 PAD13 VDDA 78 A/D Converter 1 channel 5

AN06 PAD06 VDDA 79 A/D Converter 0 channel 6

AN14 PAD14 VDDA 80 A/D Converter 1 channel 6

AN07 PAD07 VDDA 81 A/D Converter 0 channel 7

AN15 PAD15 VDDA 82 A/D Converter 1 channel 7

VDDA – 83 5.0V supply analog to digital converter

VRH VDDA 84 analog to digital converter reference high

VRL VDDA 85 analog to digital converter reference low

VSSA – 86 ground analog to digital converter

TxCAN3 PM7 VDDX 87 MSCAN3 transmit pin

RxCAN3 PM6 VDDX 88 MSCAN3 receive pin

RxD0 PS0 VDDX 89 SCI0 receive pin

TxD0 PS1 VDDX 90 SCI0 transmit pin

RxD1 PS2 VDDX 91 SCI1 receive pin

TxD1 PS3 VDDX 92 SCI1 transmit pin

MISO0 PS4 VDDX 93

Master in/slave out pin for serial peripheral

interface 0

MOSI1 PS5 VDDX 94

Master out/slave in pin for serial peripheral

interface 0

SCK0 PS6 VDDX 95 Serial clock for serial peripheral system 0

SS0 PS7 VDDX 96

Slave select output for SPI0 master mode, input for

slave mode or master mode.

VREGEN VREGEN VDDX 97 Internal Voltage Regulator Enable

TxCAN4_SCL_KWJ7 PJ7 VDDX 98 MSCAN4 transmit pin shared with IIC serial clock line

RxCAN4_SDA_KWJ6 PJ6 VDDX 99 MSCAN4 receive pin shared with IIC serial data line

TxCAN2 PM5 VDDX 100 MSCAN2 transmit pin

RxCAN2 PM4 VDDX 101 MSCAN2 receive pin

TxCAN1 PM3 VDDX 102 MSCAN1 transmit pin

RxCAN1 PM2 VDDX 103 MSCAN1 receive pin

TxCAN0_TxB PM1 VDDX 104 MSCAN1 transmit pin, shared with BDLC transmit pin

RxCAN0_RxB PM0 VDDX 105 MSCAN1 receive pin, shared with BDLC receive pin

VSSX VSSX – 106

5V I/O supply and Ground

VDDX VDDX – 107

ECS/ROMONE PK7 VDDX 108 Emulation Chip select/ROMONE function

Table 7 MC9S12DP256 Signal Description Summary

Pin Function Pin Name

Powered

Number

Description

112-pin

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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