Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Analog to Digital Converter
Block Diagram
MC9S12DP256 — Revision 1.1
Analog to Digital Converter
Block Diagram
Figure 108 ATD Module Block Diagram
+
-
COMPARATOR
CDAC
DDAC
BIAS
HV
CHARGE
PUMP
MUX
MUX
MUX
MUX
MUX
MUX
PORT
PINS
SAMPLE
AMP
IPBI
Latches
IP BUS
addr(15:0)
ctl
db(15:0)
Input
Port Reg
Data Bus
Buffers
Clock
Gen
Control
atd module clk
Result Registers
Shifter
RDAC
Rinterface Cinterface
Dinterface
SAR Register
A/D State Machine
Port
Write Port
Read
Port
S/H State Machine
Timing Gen.
Ctl
Ctl
Ctl
Ctl
Ctl
Ctl
Sample
Existing Approx.
End
Sample
Control Registers
Conversion Mode
Control Block
Clk
Clk
Clk
Prescaler
Control
Data
Ctl
Ctl
Ctl
Ctl
Ctl
Status
State
State
Ctl
MBIADB
MBIBDB
CUSTOM ANALOG
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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