Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
MSCAN
Interrupt Operation
MC9S12DP256 — Revision 1.1
MSCAN
Interrupt Operation
The MSCAN supports four interrupt vectors mapped onto eight different
interrupt sources, any of which can be individually masked (for details
see sections MSCAN Receiver Flag Register (CANRFLG) to MSCAN
Transmitter Interrupt Enable Register (CANTIER)):
•
Transmit Interrupt
: At least one of the three transmit buffers is
empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is
set.
•
Receive Interrupt
: A message is successfully received and shifted
into the foreground buffer (RxFG) of the receiver FIFO. This
interrupt is generated immediately after receiving the EOF symbol.
The RXF flag is set. If there are multiple messages in the receiver
FIFO, the RXF flag is set as soon as the next message is shifted
to the foreground buffer.
•
Wake-Up Interrupt
: Activity on the CAN bus occurred during
MSCAN internal Sleep Mode and WUPE (see MSCAN Control 0
Register (CANCTL0)) enabled.
•
Error Interrupt
: An overrun of the receiver FIFO, error or warning
condition occurred. The MSCAN Receiver Flag Register
(CANRFLG) indicates one of the following conditions:
–
Overrun:
An overrun condition of the receiver FIFO as
described in Receive Structures occurred.
–
CAN Status Change
: The actual value of the Transmit and
Receive Error Counters control the bus state of the MSCAN.
As soon as the Error Counters skip into a critical range
(Tx/Rx-Warning, Tx/Rx-Error, Bus-Off) the MSCAN flags out
an error condition. The status change, which caused the error
condition, is indicated within the TSTAT and RSTAT flags (see
Receive Structures and MSCAN Receiver Interrupt Enable
Register (CANRIER)).
–
Bus Off
: The Transmit Error Counter has exceeded 255 and
MSCAN has gone to Bus-Off state. This flag is redundant with
respect to the Can Status Change Interrupt Flag (CSCIF) flag
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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