Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 80 (14x14) 16-Bit 25 MHz I/O number 59

Table Of Contents

List of Sections
Table of Contents
General Description
- Contents
- Introduction
- Features
- MC9S12DP256 112-Pin Block Diagram
- Ordering Information
Central Processing Unit (CPU)
- Contents
- Introduction
- Programming Model
- Data Types
- Addressing Modes
- Indexed Addressing Modes
- Opcodes and Operands
- Instruction Set Summary
Pinout and Signal Description
- Contents
- MC9S12DP256 Pin Assignments in 112-pin QFP
- Power Supply Pins
- Signal Descriptions
- Port Signals
System Configuration
- Contents
- Introduction
- Modules Variabilities
- MCU Variabilities
Registers
- Contents
- Register Block
Operating Modes
- Contents
- Introduction
- Operating Modes
- Background Debug Mode
- Security
Resource Mapping
- Contents
- Introduction
- Internal Resource Mapping
- Flash EEPROM mapping through internal Memory Expansion
- Miscellaneous System Control Register
- Memory Maps
Bus Control and Input/Output
- Contents
- Introduction
- Detecting Access Type from External Signals
- Stretched Bus Cycles
- PIPE Status Signals
- Registers
Resets and Interrupts
- Contents
- Introduction
- Register Map
- Exception Priority
- Maskable interrupts
- Latching of Interrupts
- Register Descriptions
- Resets
- Effects of Reset
- Register Stacking
Voltage Regulator (VREG)
- Contents
- Overview
- Features
- Block Diagram
- Functional Description
- External Pin Connection
- Reset Initialization
- Modes of Operation
Flash EEPROM 256K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
EEPROM 4K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Interrupt Operation
Port Integration Module
- Contents
- Overview
- Block Diagram
- External Pin Descriptions
- 80 Pin QFP bond-out version
- Register Map
- Register Descriptions
- Reset Initialization
- Functional Description
- Low Power Options
- Interrupt Operation
Clocks and Reset Generator (CRG)
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Interrupt Operation
- Low Power Options
Pulse Width Modulator (PWM)
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Register Descriptions
- Functional Description
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
Enhanced Capture Timer (ECT)
- Contents
- Overview
- Features
- Modes of Operation
- Abbreviations
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Modes of Operation
- Interrupts
- Description of Interrupt Operation
Serial Communications Interface (SCI)
- Contents
- Overview
- Features
- Modes of Operation
- SCI Interface Diagram
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Modes of Operation
- Interrupt Operation
Serial Peripheral Interface (SPI)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Low Power Mode Options
- Errata
- Reset
- Interrupts
Inter-IC Bus (IIC)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- I-Bus Protocol
- Interrupt Operation
- Modes of Operation
- Programming
MSCAN
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Functional Description
- Register Descriptions
- Modes of Operation
- Low Power Options
- Interrupt Operation
Analog to Digital Converter
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Sample Conversion
- General Purpose Input Ports
Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
Background Debug Module (BDM)
- Contents
- Overview
- Interface Signals
- Registers
- Operation
- Modes of Operation
- Low-Power Options
- Interrupt Operation
Breakpoint (BKP) Module
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Descriptions
- Functional Description
- Breakpoint Operating Modes
- Breakpoint Types
- Modes of Operation
- Low Power Options
- Reset Initialization
- Interrupt Operation
- General Purpose I/O Ports
Revision History
- Changes from Rev 1.0 to Rev 1.1
Glossary
Literature Updates
- Literature Distribution Centers
- Customer Focus Center
- Microcontroller Division’s Web Site

Pinout and Signal Description

Signal Descriptions

MC9S12DP256 — Revision 1.1

Pinout and Signal Description

LSTRB_TAGLO PE3 VDDR 53

Low byte strobe (0 = low byte valid), in all modes this

pin can be used as I/O. The low strobe function is the

exclusive-NOR of A0 and the internal SZ8 signal. (The

SZ8 internal signal indicates the size 16/8 access.)

Pin function TAGLO used in instruction low byte

tagging.

R/W PE2 VDDR 54

Indicates direction of data on expansion bus. Shares

function with general-purpose I/O. Read/write in

expanded modes.

IRQ

PE1 VDDR 55

Maskable interrupt request input provides a means of

applying asynchronous interrupt requests to the MCU.

Either falling edge-sensitive triggering or

level-sensitive triggering is program selectable

(INTCR register).

XIRQ PE0 VDDR 56

The XIRQ input provides a means of requesting a

nonmaskable interrupt after reset initialization.

Because it is level sensitive, it can be connected to a

multiple-source wired-OR network.

ADDR8_DATA8 PA0 VDDR 57

External bus pins share function with general-purpose

I/O ports A. In single chip modes, the pins can be

used for general-purpose I/O. In expanded modes, the

pins are used for the external buses.

ADDR9_DATA9 PA1 VDDR 58

ADDR10_DATA10 PA2 VDDR 59

ADDR11_DATA11 PA3 VDDR 60

ADDR12_DATA12 PA4 VDDR 61

ADDR13_DATA13 PA5 VDDR 62

ADDR14_DATA14 PA6 VDDR 63

ADDR15_DATA15 PA7 VDDR 64

VDD2 VDD2 65

2.5V core supply and ground

VSS2 VSS2 66

AN00 PAD00 VDDA 67 A/D Converter 0 channel 0

AN08 PAD08 VDDA 68 A/D Converter 1 channel 0

AN01 PAD01 VDDA 69 A/D Converter 0 channel 1

AN09 PAD09 VDDA 70 A/D Converter 1 channel 1

AN02 PAD02 VDDA 71 A/D Converter 0 channel 2

AN10 PAD10 VDDA 72 A/D Converter 1 channel 2

AN03 PAD03 VDDA 73 A/D Converter 0 channel 3

AN11 PAD11 VDDA 74 A/D Converter 1 channel 3

AN04 PAD04 VDDA 75 A/D Converter 0 channel 4

AN12 PAD12 VDDA 76 A/D Converter 1 channel 4

Table 7 MC9S12DP256 Signal Description Summary

Pin Function Pin Name

Powered

Number

Description

112-pin

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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