Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

MSCAN
Low Power Options
MC9S12DP256 — Revision 1.1
MSCAN
Figure 105 Sleep Request / Acknowledge Cycle
CAUTION:
The application software must avoid setting up a transmission (by
clearing one or more TXEx flag(s)) and immediately request Sleep Mode
(by setting SLPRQ). It depends on the exact sequence of operations
whether the MSCAN starts transmitting or goes into Sleep Mode directly.
If Sleep Mode is active, the SLPRQ and SLPAK bits are set (see
Figure 105). The application software must use SLPAK as a handshake
indication for the request (SLPRQ) to go into Sleep Mode.
When in Sleep Mode (SLPRQ=1 and SLPAK=1), the MSCAN stops its
internal clocks. However, clocks to allow register accesses from the
CPU side still run. If the MSCAN is in bus-off state, it stops counting the
128*11 consecutive recessive bits due to the stopped clocks. The
TxCAN pin remains in a recessive state. If RXF=1, the message can be
read and RXF can be cleared. Shifting a new message into the
foreground buffer of the receiver FIFO (RxFG) does not take place while
in Sleep Mode. It is possible to access the transmit buffers and to clear
the associated TXE flags. No message abort takes place while in sleep
mode. If the WUPE bit in CANCLT0 is not asserted, the MSCAN will
mask any activity it detects on CAN. The RxCAN pin is therefore held
internally in a recessive state. This locks the MSCAN in Sleep Mode (see
Figure 106).
The MSCAN is only able to leave Sleep Mode (wake-up) when
• bus activity occurs and WUPE=1 or
• the MCU clears the SLPRQ bit
SYNC
SYNC
CPU Clock Domain
CAN Clock Domain
MSCAN
in Sleep Mode
CPU
Sleep Request
SLPRQ
Flag
SLPAK
Flag
SLPRQ
sync.
SLPAK
sync.
SLPRQ
SLPAK
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...