Datasheet

MSCAN
Register Descriptions
MC9S12DP256 — Revision 1.1
MSCAN
Time Stamp
Register (TSRH,
TSRL)
If the TIME bit is enabled, the MSCAN will write a special time stamp to
the respective registers in the active transmit or receive buffer as soon
as a message has been acknowledged on the CAN bus (see MSCAN
Control 0 Register (CANCTL0)). The time stamp is written on the bit
sample point for the recessive bit of the ACK delimiter in the CAN frame.
In case of a transmission, the CPU can only read the time stamp after
the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running
internal CAN bit clock. A timer overrun is not indicated by the MSCAN.
The timer is reset (all bits set to ‘0’) during Initialization Mode. The CPU
can only read the Time Stamp registers.
Read: anytime
Write: unimplemented
Address Offset: $xxxE
Bit 7 654321Bit 0
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
Write:
Reset: XXXXXXXX
Address Offset: $xxxF
Bit 7 654321Bit 0
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
Write:
Reset: XXXXXXXX
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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