Datasheet

MSCAN
MC9S12DP256 — Revision 1.1
MSCAN
Figure 103 shows the common 13 byte data structure of receive and
transmit buffers for extended identifiers. The mapping of standard
identifiers into the IDR registers is shown in Figure 104. All bits of the
receive and transmit buffers are ‘x’ out of reset because of RAM based
implementation
1
.
Addr Register Name
$00x0 Identifier Register 0
$00x1 Identifier Register 1
$00x2 Identifier Register 2
$00x3 Identifier Register 3
$00x4 Data Segment Register 0
$00x5 Data Segment Register 1
$00x6 Data Segment Register 2
$00x7 Data Segment Register 3
$00x8 Data Segment Register 4
$00x9 Data Segment Register 5
$00xA Data Segment Register 6
$00xB Data Segment Register 7
$00xC Data Length Register
$00xD
Transmit Buffer Priority Register
(1)
1. Not Applicable for Receive Buffers
$00xE
Time Stamp Register (High Byte)
(2)
2. Read-Only for CPU
$00xF
Time Stamp Register (High Byte)
(3)
3. Read-Only for CPU
Figure 102 Message Buffer Organization
1. Exception: The Transmit Priority Registers are ‘0’ out of reset
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Freescale Semiconductor, Inc.
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