Datasheet

Pinout and Signal Description
MC9S12DP256 — Revision 1.1
Pinout and Signal Description
KWH7 PH7 VDDR 32
General Purpose I/O and Interrupt
KWH6 PH6 VDDR 33
KWH5 PH5 VDDR 34
KWH4 PH4 VDDR 35
XCLKS
_NOACC PE7 VDDR 36
No Access. Indicates free cycles in expanded mode.
Selects also external clock or oscillator during reset.
Can be used as general purpose I/O pin.
IPIPE1_MODB PE6 VDDR 37 State of mode select pins during reset determine the
initial operating mode of the MCU. After reset, MODB
and MODA can be configured as instruction queue
tracking signals IPIPE1 and IPIPE0 or as
general-purpose I/O pins.
IPIPE0_MODA PE5 VDDR 38
ECLK PE4 VDDR 39
E Clock is the output connection for the external bus
clock. ECLK is used as a timing reference and for
address demultiplexing.
VSSR VSSR 40 5V Voltage Regulator and I/O Ground
VDDR VDDR 41 5V Voltage Regulator and I/O Supply
RESET RESET VDDR 42
An active low bidirectional control signal, RESET acts
as an input to initialize the MCU to a known start-up
state, and an output when COP or clock monitor
causes a reset.
VDDPLL – 43 2.5V PLL supply
XFC VDDPLL 44 External PLL Filter Capacitor
VSSPLL – 45 2.5V PLL ground
EXTAL EXTAL VDDPLL 46 Crystal driver and external clock input pins. On reset all
the device clocks are derived from the EXTAL input
frequency. XTAL is the crystal output.
XTAL XTAL VDDPLL 47
TEST_VPP TEST VDDR 48
Configures the device for various test modes including.
SCAN testing. Also the programming voltage input for
NVMs during factory test. This pin must be tied to
ground in all applications.
KWH3 PH3 VDDR 49
General Purpose I/O and Interrupt
KWH2 PH2 VDDR 50
KWH1 PH1 VDDR 51
KWH0 PH0 VDDR 52
Table 7 MC9S12DP256 Signal Description Summary
Pin Function Pin Name
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112-pin
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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