Datasheet

MSCAN
Register Descriptions
MC9S12DP256 — Revision 1.1
MSCAN
Read: anytime
Write: anytime in Initialization Mode (INITRQ=1 and INITAK=1)
AM7–AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared, this indicates that the
corresponding bit in the identifier acceptance register must be the
same as its identifier bit before a match is detected. The message is
accepted if all such bits match. If a bit is set, it indicates that the state
of the corresponding bit in the identifier acceptance register does not
affect whether or not the message is accepted.
1 = Ignore corresponding acceptance code register bit.
0 = Match corresponding acceptance code register and identifier
bits.
ProgrammerÕs
Model of Message
Storage
The following section details the organization of the receive and transmit
message buffers and the associated control registers. For reasons of
programmer interface simplification, the receive and transmit message
buffers have the same outline. Each message buffer allocates 16 bytes
in the memory map containing a 13 byte data structure. An additional
Transmit Buffer Priority Register (TBPR) is defined for the transmit
buffers. Within the last two bytes of this memory map the MSCAN stores
a special 16-bit time stamp, which is sampled from an internal timer after
successful transmission or reception of a message. This feature is only
available for transmit and receiver buffers, if the TIME bit is set (see
MSCAN Control 0 Register (CANCTL0)). The Time Stamp register is
written by the MSCAN. The CPU can only read these registers.
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